View SCAN90004-18_9102582.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

scan90004 www.ti.com snls182p ? may 2005 ? revised april 2013 scan90004 4-channel lvds buffer/repeater with pre-emphasis check for samples: scan90004 1 features description the scan90004 is a four channel 1.5 gbps lvds 2 ? 1.5 gbps maximum data rate per channel buffer/repeater. high speed data paths and flow- ? configurable pre-emphasis drives lossy through pinout minimize internal device jitter and backplanes and cables simplify board layout, while configurable pre- ? low output skew and jitter emphasis overcomes isi jitter effects from lossy backplanes and cables. the differential inputs ? lvds/cml/lvpecl compatible input, lvds interface to lvds, and bus lvds signals such as output those on ti's 10-, 16-, and 18- bit bus lvds serdes, ? on-chip 100 ? input and output termination as well as cml and lvpecl. the differential inputs ? 12 kv esd protection on lvds outputs and outputs are internally terminated with a 100 ? resistor to improve performance and minimize board ? ieee 1149.1 jtag interface space. the repeater function is especially useful for ? ieee 1149.6 limited capability boosting signals for longer distance transmission over ? fault insertion lossy cables and backplanes. ? single 3.3v supply integrated testability circuitry supports ieee1149.1 ? very low power consumption (jtag) on single-ended lvttl/cmos i/o and limited ieee1149.6 capability on high-speed ? industrial -40 to +85 c temperature range differential lvds interconnects. the 3.3v supply, ? small tqfp package footprint cmos process, and lvds i/o ensure stable high ? see ds90lv004 for non-jtag version performance at low power over the entire industrial - 40 to +85 c temperature range. typical application 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2005 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. fpga or asic lvds i/o cable or backplane fpga or asic lvds i/o scan90004
scan90004 snls182p ? may 2005 ? revised april 2013 www.ti.com block and connection diagrams figure 1. scan90004 block diagram figure 2. pinout - top view pin descriptions pin tqfp pin i/o, type description name number differential inputs in0+ 13 i, lvds channel 0 inverting and non-inverting differential inputs. in0 ? 14 in1+ 15 i, lvds channel 1 inverting and non-inverting differential inputs. in1 ? 16 in2+ 19 i, lvds channel 2 inverting and non-inverting differential inputs. in2 ? 20 in3+ 21 i, lvds channel 3 inverting and non-inverting differential inputs. in3 ? 22 differential outputs out0+ 48 o, lvds channel 0 inverting and non-inverting differential outputs. (1) out0 ? 47 out1+ 46 o, lvds channel 1 inverting and non-inverting differential outputs. (1) out1 ? 45 out2+ 42 o, lvds channel 2 inverting and non-inverting differential outputs. (1) out2 ? 41 out3+ 40 o, lvds channel 3 inverting and non-inverting differential outputs. (1) out3- 39 digital control interface pwdn 12 i, lvttl a logic low at pwdn activates the hardware power down mode. (1) the lvds outputs do not support a multidrop (blvds) environment. the lvds output characteristics of the scan90004 device have been optimized for point-to-point backplane and cable applications. 2 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: scan90004 pem0 pem1 pwdn tdo tdi tck tms trst ieee 1149.1 tap (jtag) & 1149.6 pre-emphasis and control out0+ out0- in0- in0+ out1+ out1- in1- in1+ out2+ out2- in2- in2+ out3+ out3- in3- in3+ 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 24 14 21 22 16 23 17 18 15 19 20 48 37 47 40 39 45 38 44 43 46 42 41 scan90004 (tqfp) pem0 pem1 v dd v dd v dd n/c v dd gnd gnd v dd v dd pwdn n/c tdo tdi v dd v dd n/c n/c v dd v dd tms tck trst in0+ in0- in1+ in1- gnd gnd in2+ in2- in3+ in3- gnd gnd out0+ out0- out1+ out1- gnd gnd out2+ out2- out3+ out3- gnd gnd
scan90004 www.ti.com snls182p ? may 2005 ? revised april 2013 pin descriptions (continued) pin tqfp pin i/o, type description name number pem0 1 i, lvttl pre-emphasis control inputs (affects all channels) pem1 2 tdi 34 i, lvttl test data input to support ieee 1149.1 features tdo 35 o, lvttl test data output to support ieee 1149.1 features tms 27 i, lvttl test mode select to support ieee 1149.1 features tck 26 i, lvttl test clock to support ieee 1149.1 features trst 25 i, lvttl test reset to support ieee 1149.1 features power v dd 3, 4, 5, 7, 10, 11, 28, 29, 32, 33 i, power v dd = 3.3v, 5% gnd 8, 9, 17, 18, 23, 24, 37, 38, 43, 44 i, power ground n/c 6, 30, 31, 36 no connect these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings (1) supply voltage (v dd ) ? 0.3v to +4.0v cmos input voltage -0.3v to (v dd +0.3v) lvds input voltage (2) -0.3v to (v dd +0.3v) lvds output voltage -0.3v to (v dd +0.3v) lvds output short circuit current +40 ma junction temperature +150 c storage temperature ? 65 c to +150 c lead temperature (solder, 4sec) 260 c max pkg power capacity @ 25 c 1.64w thermal resistance ( ja ) 76 c/w package derating above +25 c 13.2mw/ c esd last passing voltage (lvds output hbm, 1.5k ? , 100pf 12kv pins) eiaj, 0 ? , 200pf 250v esd last passing voltage (all other pins) hbm, 1.5k ? , 100pf 8kv eiaj, 0 ? , 200pf 250v (1) absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. ti does not recommend operation of products outside of recommended operation conditions. (2) v id max < 2.4v recommended operating conditions supply voltage (v dd ) 3.15v to 3.45v input voltage (v i ) (1) 0v to v dd output voltage (v o ) 0v to v dd operating temperature (t a ) industrial ? 40 c to +85 c (1) v id max < 2.4v copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: scan90004
scan90004 snls182p ? may 2005 ? revised april 2013 www.ti.com electrical characteristics over recommended operating supply and temperature ranges unless other specified. symbol parameter conditions min typ (1) max units lvttl dc specifications ( pwdn, pem0, pem1, tdi, tdo, tck, tms, trst) v ih high level input voltage 2.0 v dd v v il low level input voltage gnd 0.8 v i ih high level input current v in = v dd = v ddmax ? 10 +10 a i il low level input current v in = v ss , v dd = v ddmax ? 10 +10 a i ilr low level input current tdi, tms, trst -40 -200 a c in1 input capacitance any digital input pin to v ss 3.5 pf c out1 output capacitance any digital output pin to v ss 5.5 pf v cl input clamp voltage i cl = ? 18 ma ? 1.5 ? 0.8 v v oh high level output voltage i oh = ? 12 ma, v dd = 3.15 v 2.4 v (tdo) i oh = ? 100 a, v dd = 3.15 v v dd -0.2 v v ol low level output voltage i ol = 12 ma, v dd = 3.15 v 0.5 v (tdo) i ol = 100 a, v dd = 3.15 v 0.2 v i os output short circuit current tdo ? 15 ? 125 ma i oz output tri-state current tdo ? 10 +10 a lvds input dc specifications (inn ) v th differential input high threshold v cm = 0.8v to 3.4v, 0 100 mv (2) v dd = 3.45v v tl differential input low threshold v cm = 0.8v to 3.4v, ? 100 0 mv (2) v dd = 3.45v v id differential input voltage v cm = 0.8v to 3.4v, v dd = 3.45v 100 2400 mv v cmr common mode voltage range v id = 150 mv, v dd = 3.45v 0.05 3.40 v c in2 input capacitance in+ or in ? to v ss 5.2 pf i in input current v in = 3.45v, v dd = v ddmax ? 10 +10 a v in = 0v, v dd = v ddmax ? 10 +10 a lvds output dc specifications (outn ) v od differential output voltage, r l = 100 ? external resistor between out+ and 250 500 600 mv 0% pre-emphasis (2) out ? v od change in v od between -35 35 mv complementary states v os offset voltage (3) 1.05 1.18 1.475 v v os change in v os between -35 35 mv complementary states i os output short circuit current out+ or out ? short to gnd ? 60 ? 90 ma c out2 output capacitance out+ or out ? to gnd when tri-state 5.5 pf supply current (static) i cc supply current all inputs and outputs enabled and active, terminated with external differential load of 100 ? 117 140 ma between out+ and out-, 0% pre-emphasis i ccz supply current - power down pwdn = l, 0% pre-emphasis 2.7 6 ma mode switching characteristics ? lvds outputs t lht differential low to high transition use an alternating 1 and 0 pattern at 200 mb/s, 210 300 ps time measure between 20% and 80% of v od . (4) t hlt differential high to low transition 210 300 ps time (1) typical parameters are measured at v dd = 3.3v, t a = 25 c. they are for reference purposes, and are not production-tested. (2) differential output voltage v od is defined as abs(out+ ? out ? ). differential input voltage v id is defined as abs(in+ ? in ? ). (3) output offset voltage v os is defined as the average of the lvds single-ended output voltages at logic high and logic low states. (4) not production tested. specified by a statistical analysis on a sample basis at the time of characterization. 4 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: scan90004
scan90004 www.ti.com snls182p ? may 2005 ? revised april 2013 electrical characteristics (continued) over recommended operating supply and temperature ranges unless other specified. symbol parameter conditions min typ (1) max units t plhd differential low to high use an alternating 1 and 0 pattern at 200 mb/s, 2.0 3.2 ns propagation delay measure at 50% v od between input to output. t phld differential high to low 2.0 3.2 ns propagation delay t skd1 pulse skew |t plhd ? t phld | (4) 25 80 ps t skcc output channel to channel skew difference in propagation delay (t plhd or t phld ) 50 125 ps among all output channels. (4) t skp part to part skew (4) common edge, parts at same temp and v cc (4) 1.1 ns t jit jitter (0% pre-emphasis) (5) rj - alternating 1 and 0 at 750 mhz (6) 1.1 1.5 psrms dj - k28.5 pattern, 1.5 gbps (7) 43 62 psp-p tj - prbs 2 23 -1 pattern, 1.5 gbps (8) 35 85 psp-p t on lvds output enable time time from pwdn to out change from tri-state 300 ns to active. t off lvds output disable time time from pwdn to out change from active to 12 ns tri-state. switching characteristics ? scan features f max maximum tck clock frequency r l = 500 ? , 25.0 mhz c l = 35 pf t s tdi to tck, h or l 3.0 ns t h tdi to tck, h or l 0.5 ns t s tms to tck, h or l 2.5 ns t h tms to tck, h or l 0.5 ns t w tck pulse width, h or l 10.0 ns t w trst pulse width, l 2.5 ns t rec recovery time, trst to tck 1.0 ns (5) jitter is not production tested, but specified through characterization on a sample basis. (6) random jitter, or rj, is measured rms with a histogram including 1500 histogram window hits. the input voltage = v id = 500mv, 50% duty cycle at 750mhz, t r = t f = 50ps (20% to 80%). (7) deterministic jitter, or dj, is measured to a histogram mean with a sample size of 350 hits. the input voltage = v id = 500mv, k28.5 pattern at 1.5 gbps, t r = t f = 50ps (20% to 80%). the k28.5 pattern is repeating bit streams of (0011111010 1100000101). (8) total jitter, or tj, is measured peak to peak with a histogram including 3500 window hits. stimulus and fixture jitter has been subtracted. the input voltage = v id = 500mv, 2 23 -1 prbs pattern at 1.5 gbps, t r = t f = 50ps (20% to 80%). copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: scan90004
scan90004 snls182p ? may 2005 ? revised april 2013 www.ti.com feature descriptions internal terminations the scan90004 has integrated termination resistors on both the input and outputs. the inputs have a 100 ? resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the device. the lvds outputs also contain an integrated 100 ? ohm termination resistor, this resistor is used to reduce the effects of near end crosstalk (next) and does not take the place of the 100 ohm termination at the inputs to the receiving device. the integrated terminations improve signal integrity and decrease the external component count resulting in space savings. output characteristics the output characteristics of the scan90004 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. powerdown mode the pwdn input activates a hardware powerdown mode. when the powerdown mode is active ( pwdn=l), all input and output buffers and internal bias circuitry are powered off and disabled. outputs are tri-stated in powerdown mode. jtag circuitry is active per the ieee standard, but does not switch unless tck is toggling. when exiting powerdown mode, there is a delay associated with turning on bandgap references and input/output buffer circuits as indicated in the lvds output switching characteristics upon asserting the power down function ( pwdn = low), and if the pre-emphasis feature is enable, it is possible for the driver output to source current for a short amount of time lifting the output common mode to v dd . to prevent this occurrence, a load discharge pull down path can be used on either output (1 k ? to ground recommended). alternately, a commonly deployed external failsafe network will also provide this path (see input failsafe biasing ). the occurrence of this is application dependant, and parameters that will affect if this is of concern include: ac coupling, use of the powerdown feature, presence of the discharge path, presence of the failsafe biasing, the usage of the pre-emphasis feature, and input characteristics of the downstream lvds receiver. pre-emphasis pre-emphasis dramatically reduces isi jitter from long or lossy transmission media. two pins are used to select the pre-emphasis level for all outputs: off, low, medium, or high. table 1. pre-emphasis control selection table pem1 pem0 pre-emphasis 0 0 off 0 1 low 1 0 medium 1 1 high input failsafe biasing failsafe biasing of the lvds link should be considered if the downstream receiver is on and enabled when the source is in tri-state, powered off, or removed. this will set a valid known input state to the active receiver. this is accomplished by using a pull up resistor to v dd on the ? plus ? line, and a pull down resistor to gnd on the ? minus ? line. resistor values are in the 750 ? to several k ? range. the exact value depends upon the desired common mode bias point, termination resistor(s) and desired input differential voltage setting. please refer to application note an-1194 ( snla051 ) ? failsafe biasing of lvds interfaces ? for more information and a general discussion. 6 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: scan90004
scan90004 www.ti.com snls182p ? may 2005 ? revised april 2013 design-for-test (dft) features ieee 1149.1 (jtag) support the scan90004 supports a fully compliant ieee 1149.1 interface. the test access port (tap) provides access to boundary scan cells at each lvttl i/o on the device for interconnect testing. differential pins are included in the same boundary scan chain but instead contain ieee1149.6 cells. ieee1149.6 is the improved ieee standard for testing high-speed differential signals. refer to the bsdl file located on ti ? s website for the details of the scan90004 ieee 1149.1 implementation. ieee 1149.6 support ac-coupled differential interconnections on very high speed (1+ gbps) data paths are not testable using traditional ieee 1149.1 techniques. the ieee 1149.1 structures and methods are intended to test static (dc- coupled), single ended networks. ieee 1149.6 is targeted for the testing of high-speed differential (including ac coupled) networks. the scan90004 includes circuitry to support ac-coupled testing on all differential inputs and outputs and offers limited test capability. the limitations are due to several application specific factors (board layout, capacitor value, data rate etc.), and also io compliance (lvds links in general are dc coupled). the scan90004 has not been tested for full compliance or full compatibility to the ieee1149.6 standard. testing of the device in the targeted application with the appropriate jtag software will determine what extent of ieee 1149.6 support is provided by the device. fault insertion fault insertion is a technique used to assist in the verification and debug of diagnostic software. during system testing faults are "injected" to simulate hardware failure and thus help verify the monitoring software can detect and diagnose these faults. in the scan90004 an ieee1149.1 "stuck-at" instruction can create a stuck-at condition, either high or low, on any pin or combination of pins. a more detailed description of the stuck-at feature can be found in ti applications note an-1313 ( snla060 ). application information input interfacing the scan90004 accepts differential signals and allow simple ac or dc coupling. with a wide common mode range, the scan90004 can be dc-coupled with all common differential drivers (i.e. lvpecl, lvds, cml). the following three figures illustrate typical dc-coupled interface to common differential drivers. note that the scan90004 inputs are internally terminated with a 100 resistor. figure 3. typical lvds driver dc-coupled interface to scan90004 input copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: scan90004 out+ out- scan90004 receiver in+ in- 100 : differential t-line 100 : lvds driver
scan90004 snls182p ? may 2005 ? revised april 2013 www.ti.com figure 4. typical cml driver dc-coupled interface to scan90004 input figure 5. typical lvpecl driver dc-coupled interface to scan90004 input output interfacing the scan90004 outputs signals that are compliant to the lvds standard. their outputs can be dc-coupled to most common differential receivers. figure 6 illustrates typical dc-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. while most differential receivers have a common mode input range that can accommodate lvds compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. figure 6. typical scan90004 output dc-coupled interface to an lvds, cml or lvpecl receiver 8 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: scan90004 out+ out- 50 : 50 : v cc cml3.3v or cml2.5v driver 100 : differential t-line scan90004 receiver in+ in- 100 : out+ out- 150-250 : 100 : differential t-line lvds receiver in+ in- 100 : lvpecl driver 150-250 : out+ out- cml or lvpecl or lvds in+ in- 100 : 100 : differential t-line differential receiver scan90004 driver 100 :
scan90004 www.ti.com snls182p ? may 2005 ? revised april 2013 typical performance characteristics power supply current total jitter (t j ) vs. vs. bit data rate bit data rate dynamic power supply current was measured while total jitter measured at 0v differential while running a clock or prbs 2 23 -1 pattern running a prbs 2 23 -1 pattern with all 4 channels active. with a single channel active. v cc = 3.3v, t a = +25 c, v id = 0.5v, v cm = 1.2v v cc = 3.3v, t a = +25 c, v id = 0.5v, 0% pre-emphasis figure 7. figure 8. total jitter (u.i.) total jitter (u.i.) vs. vs. bit data rate bit data rate scan90004 as driver scan90004 as receiver total jitter measured while scan90004 output is total jitter measured at scan90004 receiver outputs driving a prbs 2 7 -1 nrz pattern after receiving a prbs 2 7 -1 nrz pattern with a single active channel across a belden 1700a cable. over the specified cable length. v cc = 3.3v, t a = +25 c, v id = 0.5v, 0% pre-emphasis. v cc = 3.3v, t a = +25 c, v id = 0.5v, data measured at end of specified cable length. data collected at receiver outputs, receiver located at end of specified belden 1700a cable length. figure 9. figure 10. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: scan90004 total jitter - t j (ps) 120 0 bit data rate (gbps) 0 0.5 1.0 1.5 2.0 20 40 60 80 100 vcm = 0.25v vcm = 0.5v vcm = 1.2v vcm = 3.05v vcm = 2.4v power supply current (ma) 350 0 bit data rate (gbps) 0 0.25 0.5 0.75 1.0 1.5 50 100 150 200 250 300 1.25 prbs-23, 0% pre prbs-23, max pre clock, 0% pre clock, max pre
scan90004 snls182p ? may 2005 ? revised april 2013 www.ti.com typical performance characteristics (continued) total jitter (t j ) positive edge transition vs. vs. temperature pre-emphasis level total jitter measured at 0v differential while running a prbs 2 23 -1 pattern with a single channel active. v cc = 3.3v, v id = 0.5v, v cm = 1.2v, 1.5 gbps data rate, 0% pre-emphasis figure 11. figure 12. 10 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: scan90004 total jitter - t j (ps) 80 0 temperature (c) -40 0 40 60 100 10 20 30 60 70 50 40 -20 20 80 100 mv/div 200 ps/div 100% 50% 25% 0%
scan90004 www.ti.com snls182p ? may 2005 ? revised april 2013 revision history changes from revision o (april 2013) to revision p page ? changed layout of national data sheet to ti format .......................................................................................................... 10 copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: scan90004
package option addendum www.ti.com 17-jan-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples scan90004tvs/nopb active tqfp pfb 48 250 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 85 scan 90004tvs (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
mechanical data mtqf019a january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 pfb (s-pqfp-g48) plastic quad flatpack 4073176 / b 10/96 gage plane 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 0,17 0,27 24 25 13 12 sq 36 37 7,20 6,80 48 1 5,50 typ sq 8,80 9,20 1,05 0,95 1,20 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
important notice texas instruments incorporated (ti) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. ti ? s published terms of sale for semiconductor products ( http://www.ti.com/sc/docs/stdterms.htm ) apply to the sale of packaged integrated circuit products that ti has qualified and released to market. additional terms may apply to the use or sale of other types of ti products and services. reproduction of significant portions of ti information in ti data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such reproduced documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyers and others who are developing systems that incorporate ti products (collectively, ? designers ? ) understand and agree that designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that designers have full and exclusive responsibility to assure the safety of designers ' applications and compliance of their applications (and of all ti products used in or for designers ? applications) with all applicable regulations, laws and other applicable requirements. designer represents that, with respect to their applications, designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. designer agrees that prior to using or distributing any applications that include ti products, designer will thoroughly test such applications and the functionality of such ti products as used in such applications. ti ? s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, ? ti resources ? ) are intended to assist designers who are developing applications that incorporate ti products; by downloading, accessing or using ti resources in any way, designer (individually or, if designer is acting on behalf of a company, designer ? s company) agrees to use any particular ti resource solely for this purpose and subject to the terms of this notice. ti ? s provision of ti resources does not expand or otherwise alter ti ? s applicable published warranties or warranty disclaimers for ti products, and no additional obligations or liabilities arise from ti providing such ti resources. ti reserves the right to make corrections, enhancements, improvements and other changes to its ti resources. ti has not conducted any testing other than that specifically described in the published documentation for a particular ti resource. designer is authorized to use, copy and modify any individual ti resource only in connection with the development of applications that include the ti product(s) identified in such ti resource. no other license, express or implied, by estoppel or otherwise to any other ti intellectual property right, and no license to any technology or intellectual property right of ti or any third party is granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti products or services are used. information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. use of ti resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. ti resources are provided ? as is ? and with all faults. ti disclaims all other warranties or representations, express or implied, regarding resources or use thereof, including but not limited to accuracy or completeness, title, any epidemic failure warranty and any implied warranties of merchantability, fitness for a particular purpose, and non-infringement of any third party intellectual property rights. ti shall not be liable for and shall not defend or indemnify designer against any claim, including but not limited to any infringement claim that relates to or is based on any combination of products even if described in ti resources or otherwise. in no event shall ti be liable for any actual, direct, special, collateral, indirect, punitive, incidental, consequential or exemplary damages in connection with or arising out of ti resources or use thereof, and regardless of whether ti has been advised of the possibility of such damages. unless ti has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., iso/ts 16949 and iso 26262), ti is not responsible for any failure to meet such industry standard requirements. where ti specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. using products in an application does not by itself establish any safety features in the application. designers must ensure compliance with safety-related requirements and standards applicable to their applications. designer may not use any ti products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). such equipment includes, without limitation, all medical devices identified by the u.s. food and drug administration as class iii devices and equivalent classifications outside the u.s. ti may expressly designate certain products as completing a particular qualification (e.g., q100, military grade, or enhanced product). designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at designers ? own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

▲Up To Search▲

Price & Availability of SCAN90004-18

	To Download SCAN90004-18 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .